#ifndef CYGONCE_PKGCONF_IO_SERIAL_CORTEXM_STM32_H
#define CYGONCE_PKGCONF_IO_SERIAL_CORTEXM_STM32_H
/*
 * File <pkgconf/io_serial_cortexm_stm32.h>
 *
 * This file is generated automatically by the configuration
 * system. It should not be edited. Any changes to this file
 * may be overwritten.
 */

#define CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL1 1
#define CYGDAT_IO_SERIAL_CORTEXM_STM32_SERIAL1_NAME "/dev/ser1"
#define CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL1_BAUD 115200
#define CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL1_BAUD_115200
#define CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL1_BUFSIZE 1024
#define CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL1_BUFSIZE_1024
#define CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL3 1
#define CYGDAT_IO_SERIAL_CORTEXM_STM32_SERIAL3_NAME "/dev/ser3"
#define CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL3_BAUD 115200
#define CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL3_BAUD_115200
#define CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL3_BUFSIZE 128
#define CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL3_BUFSIZE_128
#define CYGPKG_IO_SERIAL_CORTEXM_STM32_OPTIONS 1
#define CYGPKG_IO_SERIAL_CORTEXM_STM32_TESTING 1
#define CYGPRI_SER_TEST_CRASH_ID "stm32"
#define CYGPRI_SER_TEST_SER_DEV "/dev/ser1"
#define CYGPRI_SER_TEST_TTY_DEV "/dev/tty1"

#endif
